One of the mixers is used for the voltage measurement and the other for the current measurement. The ratio of the two corresponds to the impedance we want to measure. Both the magnitude and phase are measured. In the bridge a voltage across one resistor is proportional to the voltage being applied to the circuit under test and the voltage across another resistor is proportional to the current flowing into the circuit connected to the analyzer’s test port. These high frequency components consist of aliases at multiples of the internal clock frequency as well as other spurs.įor impedance measurement a resistive bridge is used because of its simplicity and good frequency response, working down to DC. These filters reduce the level of spurious high frequency components that appear in the output of the DDS. The output of each amplifier is followed by elliptic low pass filters with a cut-off frequency of 230 MHz. Most DDS designs use a broadband balun transformer to convert to single end mode but because of the restricted height available in the SARK110 enclosure a silicon-based solution was chosen. The output of each of the DDS channels is differential and is amplified by a dual high speed current feedback amplifier working in differential input mode and with output in single ended mode. The SARK-110 software compensates for this amplitude rolloff effect by using the capability of the DDS to adjust the amplitude level of the output signal, so the analyzer maintains a flat output amplitude. The amplitude level of the DDS channel’s output is frequency dependent and it is reduced with increasing frequency following a SIN(X)/X function. In general the DDS can be configured to generate a frequency of up to one third of the clock frequency but in this design, due to the external reconstruction filter, it is possible to achieve an output frequency of up to 230 MHz. The DDS has an internal oscillator driven by an external 24 MHz crystal and is able to multiply this clock internally by a user configurable factor of 4 to 20, so the maximum internal clock frequency is 480 MHz. One of the DDS channels operates at the specified test frequency and the other is programmed to operate just 1 kHz above it, which is the value of the intermediate frequency. The signal generator is provided by a single chip dual direct digital synthesizer (DDS) AD9958 from Analog Devices, which generates a sinusoidal signal for impedance measurement and a local oscillator signal for the tuned receivers (mixers).
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